Sovereign, auditable RISC-V — on a path to European silicon.
Logifive designs RISC-V processor cores and post-quantum security IP for a Europe that wants to own its computing base — and be able to prove what that silicon does. Two ideas drive everything we build: sovereignty, so the architecture, the RTL and the keys stay in European hands rather than depending on foreign proprietary cores; and auditability, so trust comes from inspection, not assertion — the design is open to examine, and every correctness claim can be re-run.
The Product Family
Our first core, LX3, is a compact RISC-V CPU taken from RTL to synthesis and checked correct six independent ways — reference co-simulation, ISA-model step-lock, bounded formal proof, the official RISC-V compliance suite, gate-level simulation, and live JTAG debug. The RTL is open and every result is reproducible from the scripts in the public repository: you don't have to take our word for any of it. That is the standard we hold every future design to.
LX3
32-bit RISC-V Embedded Core
Available today · open source (Apache-2.0). A 3-stage in-order RV32IMC core with the machine/user privilege set, physical memory protection, debug, and a full six-rail verification report. Real synthesis numbers on open PDKs, presented honestly.
LA6
64-bit Dual Issue Application Core
In development · licensable IP. A dual-issue, 6-stage, in-order RV64GC core with an Sv39 MMU, designed to boot upstream Linux — carrying LX3's verification discipline into an application-class design. Architecture fixed; verification harness built before the RTL. Vector (RVV 1.0) and multicore on the roadmap. Performance figures are targets.
LP12
64-bit Out of Order Performance Core
In design · licensable IP. A 64-bit out-of-order superscalar core for higher single-thread performance and virtualization. Currently in architecture exploration; all figures are design targets.
XPQC
Post-Quantum Crypto Coprocessor
In development · licensable IP. A dual-issue, 6-stage, in-order RV64GC core with an Sv39 MMU, designed to boot upstream Linux — carrying LX3's verification discipline into an application-class design. Architecture fixed; verification harness built before the RTL. Vector (RVV 1.0) and multicore on the roadmap. Performance figures are targets.